An Alternative FPGA Implementation of Decoders for Quasi-Cyclic LDPC Codes

Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes

In this paper we propose the construction of Spatially Coupled Low-Density Parity-Check (SC-LDPC) codes using a Quasi-Cyclic (QC) algorithm. The QC based approach is optimized to obtain memory efficiency in storing the parity-check matrix in the decoders. A hardware model of the parity-check storage units has been designed for Xilinx FPGA to compare the logic and memory requirements for various...

A Memory Efficient FPGA Implementation of Quasi-Cyclic LDPC Decoder

Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents an implementation of Quasi-Cyclic Low-Density Parity-Check decoder by using FPGA. Modified Min-Sum decoding algorithm is applied to reduce the memor...

FPGA Implementations of LDPC over GF(2m) Decoders

Low Density Parity Check (LDPC) codes over GF(2) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there is a substantial lack of hardware implementations for LDPC over GF(2) codes. This paper presents a FPGA serial implem...

Fully programmable LDPC decoder hardware architectures

In recent years, the amount of digital data which is stored and transmitted for private and public usage has increased considerably. To allow a save transmission and storage of data despite of error-prone transmission media, error correcting codes are used. A large variety of codes has been developed, and in the past decade low-density parity-check (LDPC) codes which have an excellent error cor...

On the Grobner Basis of a Family of Quasi-Cyclic LDPC Codes